The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 2018
Filed:
May. 19, 2015
Applicant:
Linear Algebra Technologies Limited, Dublin, IE;
Inventor:
Richard Richmond, Belfast, GB;
Assignee:
LINEAR ALGEBRA TECHNOLOGIES LIMITED, Dublin, IE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0884 (2016.01); G06F 12/0804 (2016.01); G06F 12/0842 (2016.01); G06F 12/0875 (2016.01); G06F 12/0895 (2016.01); G06F 12/0811 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0884 (2013.01); G06F 12/0804 (2013.01); G06F 12/0811 (2013.01); G06F 12/0842 (2013.01); G06F 12/0875 (2013.01); G06F 12/0895 (2013.01); G06F 2212/283 (2013.01); G06F 2212/455 (2013.01);
Abstract
Cache memory mapping techniques are presented. A cache may contain an index configuration register. The register may configure the locations of an upper index portion and a lower index portion of a memory address. The portions may be combined to create a combined index. The configurable split-index addressing structure may be used, among other applications, to reduce the rate of cache conflicts occurring between multiple processors decoding the video frame in parallel.