The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 2018
Filed:
Oct. 23, 2014
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
William L. Walker, Fort Collins, CO (US);
Paul J. Moyer, Fort Collins, CO (US);
Richard M. Born, Fort Collins, CO (US);
Eric Morton, Austin, TX (US);
David Christie, Austin, TX (US);
Marius Evers, Sunnyvale, CA (US);
Scott T. Bingham, Sunnyvale, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A method and apparatus for performing a bus lock and a translation lookaside buffer invalidate transaction includes receiving, by a lock master, a lock request from a first processor in a system. The lock master sends a quiesce request to all processors in the system, and upon receipt of the quiesce request from the lock master, all processors cease issuing any new transactions and issue a quiesce granted transaction. Upon receipt of the quiesce granted transactions from all processors, the lock master issues a lock granted message that includes an identifier of the first processor. The first processor performs an atomic transaction sequence and sends a first lock release message to the lock master upon completion of the atomic transaction sequence. The lock master sends a second lock release message to all processors upon receiving the first lock release message from the first processor.