The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 13, 2018

Filed:

Jan. 05, 2016
Applicant:

Lenovo Enterprise Solutions (Singapore) Pte. Ltd., Singapore, SG;

Inventors:

Paul D. Kangas, Raleigh, NC (US);

Dustin Patterson, Durham, NC (US);

Mehul Shah, Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/273 (2006.01); G06F 11/22 (2006.01);
U.S. Cl.
CPC ...
G06F 11/273 (2013.01); G06F 11/2236 (2013.01);
Abstract

A system includes a CPU including a primary address decode logic module (PADLM) and a plurality of diagnostic registers, wherein the PADLM includes address bus inputs, and an enable input port. The system further includes a data flip-flop having a data input coupled to a master enable signal line, a set input coupled to an interrupt signal line, an output coupled to the enable input port of the PADLM, and a clock input. Still further, the system includes an address decode logic module having a memory address input and an output indicating whether the memory address is within a predetermined address range of the diagnostic registers, wherein the output of the address decode logic module is coupled to the clock input. Memory mapping is enabled in response to receiving an interrupt signal and determining that the memory address is within a predetermined range of memory addresses for diagnostic registers.


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