The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 13, 2018

Filed:

Sep. 08, 2015
Applicant:

Imagination Technologies Limited, Kings Langley, GB;

Inventors:

Michael John Davis, Bath, GB;

Adrian John Anderson, Chepstow, GB;

Gary Christopher Wass, St Albans, GB;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 9/30 (2006.01); G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0638 (2013.01); G06F 3/061 (2013.01); G06F 3/0673 (2013.01); G06F 9/30043 (2013.01); G06F 9/38 (2013.01); G06F 12/02 (2013.01); G06F 12/0207 (2013.01); G06F 2212/1028 (2013.01); G06F 2212/1041 (2013.01); Y02B 60/1225 (2013.01);
Abstract

Methods and apparatus for efficient loading of data from memory to registers and storing of data from registers to memory are described. In an embodiment, a processor comprises a data structure to which addresses which are used for load operations are pushed. Instead of independently generating addresses for a store operation, addresses are popped from the data structure and either used directly or an optional offset may first be applied to the popped address. In this way, a store operation and a load operation may be performed in parallel because they do not both require use of the logic which independently generates addresses for load/store operations. In various examples, the data structure is a FIFO structure.


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