The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 06, 2018

Filed:

Jun. 29, 2016
Applicants:

Tamon Sadasue, Kanagawa, JP;

Yasuhiro Kajiwara, Kanagawa, JP;

Kazuhiro Takazawa, Tokyo, JP;

Kazufumi Matsushita, Kanagawa, JP;

Yasuko Shirataka, Kanagawa, JP;

Yasuko Hashimoto, Kanagawa, JP;

Satoshi Aoki, Kanagawa, JP;

Inventors:

Tamon Sadasue, Kanagawa, JP;

Yasuhiro Kajiwara, Kanagawa, JP;

Kazuhiro Takazawa, Tokyo, JP;

Kazufumi Matsushita, Kanagawa, JP;

Yasuko Shirataka, Kanagawa, JP;

Yasuko Hashimoto, Kanagawa, JP;

Satoshi Aoki, Kanagawa, JP;

Assignee:

Ricoh Company, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 25/00 (2006.01); H04J 3/06 (2006.01); H04L 12/40 (2006.01); H04N 21/242 (2011.01); H04N 21/43 (2011.01); H04L 29/06 (2006.01);
U.S. Cl.
CPC ...
H04J 3/0658 (2013.01); H04L 12/40078 (2013.01); H04N 21/242 (2013.01); H04N 21/4305 (2013.01); H04L 65/80 (2013.01);
Abstract

A reception apparatus for receiving data from a transmission apparatus includes a data receiver configured to receive a synchronization packet including clock information generated by the transmission apparatus and data from the transmission apparatus, a storage memory, storing the received data, a clock adjuster configured to correct a clock of the reception apparatus based on a deviation between a clock of the transmission apparatus and the clock of the reception apparatus by using the clock information generated by the transmission apparatus, a controller configured to control a clock correction amount of the clock adjuster based on a storage amount of data in the storage memory, and a data output circuit configured to retrieve the data from the storage memory to output the retrieved data in synchronization with the corrected clock.


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