The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 06, 2018

Filed:

Jan. 10, 2017
Applicant:

Entropic Communications, Llc, Carlsbad, CA (US);

Inventors:

Branislav Petrovic, Carlsbad, CA (US);

Tommy Yu, Carlsbad, CA (US);

Troy Brandon, Carlsbad, CA (US);

Ralph Duncan, Carlsbad, CA (US);

Assignee:

Entropic Communications, LLC, Carlsbad, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/00 (2006.01); H03M 1/12 (2006.01); H03B 5/30 (2006.01); H03B 5/18 (2006.01); H04N 5/445 (2011.01); H04N 5/44 (2011.01); H04H 40/90 (2008.01);
U.S. Cl.
CPC ...
H03M 1/1245 (2013.01); H03B 5/1876 (2013.01); H03B 5/30 (2013.01); H03M 1/00 (2013.01); H03M 1/12 (2013.01); H04H 40/90 (2013.01); H04N 5/4401 (2013.01); H04N 5/44543 (2013.01);
Abstract

Methods and systems for frequency generation may comprise a circuit with a first input coupled to receive a first satellite signal at a first satellite downlink frequency, a second input coupled to receive a second satellite signal at a second satellite downlink frequency, and a first analog-to-digital converter (ADC) having an input coupled to receive the first satellite signal. The first ADC may be configured to create a first digital output signal representing the first satellite signal. A second ADC having an input coupled to receive the second satellite signal may be configured to create a second digital output representing the second satellite signal. The circuit may comprise a dielectric resonator oscillator having an output and a clock generator circuit having an input coupled to the oscillator output and configured to output one or more clocks used by the first and second ADCs.


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