The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 06, 2018

Filed:

Dec. 07, 2016
Applicant:

Analog Devices, Inc., Norwood, MA (US);

Inventors:

Hongxing Li, Andover, MA (US);

Michael Mueck, Andover, MA (US);

Michael C. W. Coln, Lexington, MA (US);

Assignee:

Analog Devices, Inc., Norwood, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/12 (2006.01); H03M 1/10 (2006.01); H03M 1/46 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1009 (2013.01); H03M 1/1245 (2013.01); H03M 1/466 (2013.01);
Abstract

Various techniques that can provide a capability to background calibrate ADC linearity error, e.g., due to capacitor mismatch drift and other parameter drift, during normal ADC operation in which analog-to-digital signal conversions are ongoing. A method can include grouping capacitors of an ADC into multiple clusters and calibrating under an arbitrary signal condition. To quickly converge the calibration result, the same arbitrary signal can be converted twice, and the capacitor(s) being calibrated can be modulated after first conversion. The difference between the results of the first and second conversions can contain the error information that can be used for calibration, and the signal component can be removed by this process. These techniques can provide improved linearity at 20-bit level and beyond.


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