The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 06, 2018

Filed:

Jul. 18, 2016
Applicant:

Cambridge Electronics, Inc., Cambridge, MA (US);

Inventors:

Ling Xia, Belmont, MA (US);

Mohamed Azize, Medford, MA (US);

Bin Lu, Watertown, MA (US);

Assignee:

Cambridge Electronics, Inc., Cambridge, MA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/86 (2006.01); H01L 49/02 (2006.01); H01L 29/861 (2006.01); H01L 29/778 (2006.01); H01L 29/94 (2006.01); H01L 29/20 (2006.01); H01L 29/45 (2006.01); H01L 29/417 (2006.01); H01L 29/47 (2006.01);
U.S. Cl.
CPC ...
H01L 29/404 (2013.01); H01L 28/40 (2013.01); H01L 29/402 (2013.01); H01L 29/405 (2013.01); H01L 29/7786 (2013.01); H01L 29/861 (2013.01); H01L 29/94 (2013.01); H01L 29/2003 (2013.01); H01L 29/41766 (2013.01); H01L 29/4236 (2013.01); H01L 29/42316 (2013.01); H01L 29/452 (2013.01); H01L 29/475 (2013.01);
Abstract

Field-plate structures are disclosed for electrical field management in semiconductor devices. A field-plate semiconductor structure includes a semiconductor substrate, a source ohmic contact, a drain ohmic contact, and a gate contact disposed over a gate region between the source ohmic contact and the drain ohmic contact, and a source field plate connected to the source ohmic contact. A field-plate dielectric is disposed over the semiconductor substrate. An encapsulating dielectric is disposed over the gate contact, wherein the encapsulating dielectric covers a top surface of the gate contact. The source field plate is disposed over the field-plate dielectric in a field plate region, from which the encapsulating dielectric is absent.


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