The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 06, 2018
Filed:
Jan. 15, 2016
Applicant:
Jaegoo Lee, Suwon-si, KR;
Inventor:
Jaegoo Lee, Suwon-si, KR;
Assignee:
SAMSUNG ELECTRONICS CO., LTD., Gyeonggi-Do, KR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 27/088 (2006.01); H01L 23/528 (2006.01); H01L 27/115 (2017.01); H01L 27/11582 (2017.01); H01L 27/11551 (2017.01); H01L 27/11556 (2017.01); H01L 27/11578 (2017.01); H01L 27/11548 (2017.01); H01L 27/11575 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 23/528 (2013.01); H01L 27/11548 (2013.01); H01L 27/11551 (2013.01); H01L 27/11556 (2013.01); H01L 27/11575 (2013.01); H01L 27/11578 (2013.01); H01L 2924/0002 (2013.01);
Abstract
Semiconductor memory devices may include a semiconductor substrate, a first stack disposed on the semiconductor substrate and a second stack disposed on the first stack. The first stack may include a plurality of first word lines with a plurality of first line pads stacked in a stair form, and the second stack may include a plurality of second word lines with a plurality of second line pads stacked in a stair form. The second stack may be shifted on the first stack such that sides of the plurality of first word line pads are exposed.