The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 27, 2018

Filed:

Sep. 03, 2013
Applicant:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Jean-Paul Garandet, Le Bourget du Lac, FR;

Nicolas Chaintreuil, Montmelian, FR;

Annalaura Fasiello, Milan, IT;

Eric Pilat, Brison-Saint-Innocent, FR;

Yannick Veschetti, Concarneau, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C30B 15/04 (2006.01); H01L 31/047 (2014.01); C30B 29/06 (2006.01); H01L 31/0352 (2006.01); H01L 31/068 (2012.01); H01L 31/18 (2006.01); H01L 31/0288 (2006.01); H01L 31/0687 (2012.01);
U.S. Cl.
CPC ...
H01L 31/047 (2014.12); C30B 15/04 (2013.01); C30B 29/06 (2013.01); H01L 31/0288 (2013.01); H01L 31/03529 (2013.01); H01L 31/068 (2013.01); H01L 31/0687 (2013.01); H01L 31/1804 (2013.01); H01L 31/1876 (2013.01); Y02E 10/547 (2013.01); Y02P 70/521 (2015.11);
Abstract

The present invention relates to a method for manufacturing a monolithic silicon wafer () comprising multiple vertical junctions () having an alternation of n-doped areas and p-doped areas, including at least the steps of: (i) providing a liquid bath () including silicon, at least one n-type doping agent and at least one p-type doping agent; (ii) proceeding to directionally solidify the silicon in a direction (I), varying the convection-diffusion parameters thereof in order to alternate the growth of n-doped silicon layers () and p-doped silicon layers (); and (iii) cutting a slice (), parallel to the direction (I), of the multi-layer structure obtained at the end of the step (ii), such as to obtain said expected wafer ().


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