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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9905555 B1

PDFFull Text
Date of Patent:
Feb. 27, 2018

Filed:

Oct. 27, 2016

Semiconductor device and semiconductor device manufacturing method

Applicant:

Fuji Electric Co., Ltd., Kanagawa, JP;

Inventors:

Tatsuya Naito, Matsumoto, JP;

Masahito Otsuki, Matsumoto, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kanagawa, JP;

Attorney:
Primary Examiner:

Vu A Vu

Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 27/06 (2006.01); H01L 21/8234 (2006.01); H01L 21/265 (2006.01); H01L 21/322 (2006.01); H01L 29/739 (2006.01); H01L 29/78 (2006.01); H01L 27/04 (2006.01); H01L 27/08 (2006.01); H01L 27/088 (2006.01); H01L 29/861 (2006.01); H01L 29/868 (2006.01); H01L 29/06 (2006.01); H01L 21/304 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0623 (2013.01); H01L 21/265 (2013.01); H01L 21/304 (2013.01); H01L 21/322 (2013.01); H01L 21/8234 (2013.01); H01L 27/04 (2013.01); H01L 27/08 (2013.01); H01L 27/088 (2013.01); H01L 29/06 (2013.01); H01L 29/0619 (2013.01); H01L 29/0634 (2013.01); H01L 29/739 (2013.01); H01L 29/7395 (2013.01); H01L 29/78 (2013.01); H01L 29/861 (2013.01); H01L 29/868 (2013.01);
Abstract

An SJ-MOSFET and IGBT are provided in a single semiconductor chip. Furthermore, a balance is made between a carrier amount of n-type columns and a carrier amount of p-type columns, to encourage formation of a depletion layer in when a reverse voltage is applied in the SJ-MOSFET section. Provided is a includes a semiconductor substrate, a super junction structure formed on a front surface side of the semiconductor substrate, and a field stop layer formed at a position overlapping with the super junction structure on a back surface side of the semiconductor substrate, in a manner to not contact an end of the super junction structure on the back surface side.

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