The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 27, 2018
Filed:
Mar. 26, 2015
Applicant:
Denso Corporation, Kariya, Aichi-pref., JP;
Inventors:
Hiroshi Ishino, Kariya, JP;
Tomokazu Watanabe, Kariya, JP;
Assignee:
DENSO CORPORATION, Kariya, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/07 (2006.01); H01L 23/367 (2006.01); H01L 25/18 (2006.01); H01L 23/492 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 23/04 (2006.01); H01L 23/00 (2006.01); H02M 7/5387 (2007.01); H02P 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 25/072 (2013.01); H01L 23/04 (2013.01); H01L 23/3121 (2013.01); H01L 23/3675 (2013.01); H01L 23/492 (2013.01); H01L 23/49838 (2013.01); H01L 24/48 (2013.01); H01L 25/18 (2013.01); H02M 7/5387 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/33181 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48106 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/73215 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/1203 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01); H02P 27/06 (2013.01);
Abstract
A semiconductor module includes upper arms and lower arms for three phases, heat sinks, a main circuit side bus bar, an output terminal side bus bar, a control terminal, and a resin mold portion. The output terminal side bus bar includes U-phase to W-phase wiring layers disposed opposite to each other via an insulating layer and U to W terminals electrically connecting each of the U-phase to W-phase wiring layer and a load. A stacked layer number of the U-phase to W-phase wiring layer is set to be an even number.