The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 27, 2018

Filed:

Mar. 02, 2016
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Kenji Sakata, Tokyo, JP;

Tsuyoshi Kida, Tokyo, JP;

Yoshihiro Ono, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 24/81 (2013.01); H01L 24/16 (2013.01); H01L 24/27 (2013.01); H01L 24/75 (2013.01); H01L 24/92 (2013.01); H01L 25/0652 (2013.01); H01L 24/13 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/83 (2013.01); H01L 2224/1146 (2013.01); H01L 2224/11849 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/2732 (2013.01); H01L 2224/27436 (2013.01); H01L 2224/73104 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/7565 (2013.01); H01L 2224/75251 (2013.01); H01L 2224/75305 (2013.01); H01L 2224/75745 (2013.01); H01L 2224/8121 (2013.01); H01L 2224/81022 (2013.01); H01L 2224/8183 (2013.01); H01L 2224/81132 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81203 (2013.01); H01L 2224/81355 (2013.01); H01L 2224/81444 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/81862 (2013.01); H01L 2224/81986 (2013.01); H01L 2224/83191 (2013.01); H01L 2224/83192 (2013.01); H01L 2224/83862 (2013.01); H01L 2224/9205 (2013.01); H01L 2224/92125 (2013.01); H01L 2224/97 (2013.01);
Abstract

A method for manufacturing a semiconductor device includes the steps of mounting a Si interposer over a printed wiring substrate, plasma-cleaning an upper surface of the Si interposer, disposing an NCF over the upper surface of the Si interposer, and mounting a semiconductor chip over the upper surface of the Si interposer through the NCF. Also, the method includes the step of electrically coupling each of plural electrodes of a second substrate and each of plural electrode pads of the semiconductor chip with each other through plural bump electrodes by reflow, and the surface of the Si interposer is plasma-cleaned before attaching the NCF to the Si interposer.


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