The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 27, 2018

Filed:

Feb. 05, 2016
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Toshifumi Iwasaki, Ibaraki, JP;

Yukio Maki, Ibaraki, JP;

Assignee:

Renesas Electronics Corporation, Koutou-Ku, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 27/06 (2006.01); H01L 23/52 (2006.01); H01L 21/76 (2006.01); H01L 27/02 (2006.01); H01L 27/08 (2006.01); H01L 27/10 (2006.01); H01L 23/525 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5256 (2013.01); H01L 21/76801 (2013.01); H01L 21/76831 (2013.01); H01L 27/11 (2013.01);
Abstract

An object of the invention is to provide a semiconductor device having less cracking or peeling and a method of manufacturing the same. A fuse portion of a semiconductor device has bit lines electrically coupled to a SRAM memory cell. The bit lines are covered by an interlayer insulating film. As the interlayer insulating film, a boron-doped BPTEOS film is formed. The bit lines have thereabove a fuse. The fuse and the bit lines are electrically coupled to each other via contact plugs. The interlayer insulating film that covers the bit lines therewith is separated from the contact plugs.


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