The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 27, 2018

Filed:

Jan. 24, 2017
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Prokash Ghosh, Mogra, IN;

Sourav Roy, Kolkata, IN;

Neha Raj, Ghaziabad, IN;

Assignee:

NXP B.V., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
G11C 29/70 (2013.01); G11C 5/06 (2013.01);
Abstract

An error-resilient memory device includes sets of memory blocks and redundant memory blocks for storing a set of data bits. A memory block includes a set of memory cells, each memory cell is adjacent to at least two other memory cells, and a memory block is formed by a matrix of the set of memory cells. In a row-folded implementation, a word line is connected to each memory cell, and a set of bit lines is connected to the corresponding set of memory cells. In a column-folded implementation, a bit line is connected to each memory cell, and a set of word lines is connected to the corresponding set of memory cells. A redundant memory block is used to store the set of data bits when the memory block includes a fault.


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