The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 27, 2018

Filed:

Sep. 23, 2016
Applicants:

Pil Seon Yoo, Seoul, KR;

Ji-sang Lee, Iksan-si, KR;

Gyosoo Choo, Yongin-si, KR;

Inventors:

Pil Seon Yoo, Seoul, KR;

Ji-Sang Lee, Iksan-si, KR;

Gyosoo Choo, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/24 (2006.01); G11C 16/28 (2006.01); G11C 16/34 (2006.01); G11C 16/32 (2006.01); G11C 16/30 (2006.01); G11C 7/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/24 (2013.01); G11C 7/04 (2013.01); G11C 16/28 (2013.01); G11C 16/30 (2013.01); G11C 16/32 (2013.01); G11C 16/3418 (2013.01); G11C 16/3459 (2013.01);
Abstract

A nonvolatile memory device includes a memory cell, a bit line, a page buffer, and a control logic. The page buffer is connected to the memory cell through the bit line and the page buffer is configured to precharge the bit line to perform a desired operation. The desired operation may be one of a read operation and a verify operation. The control logic is configured to control bit line development time differently according to a temperature after precharging the bit line during the desired operation. The control logic is configured to determine the bit line development time according to a period of a reference clock signal that includes a different frequency depending on the temperature and/or a temperature compensation pulse signal including a pulse width that varies based on the temperature.


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