The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 27, 2018
Filed:
Jun. 18, 2015
Applicant:
Mediatek Inc., Hsin-Chu, TW;
Inventor:
Jia-Wei Fang, Hsinchu, TW;
Assignee:
MEDIATEK INC., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5072 (2013.01); G06F 17/5077 (2013.01); G06F 17/5081 (2013.01); G06F 17/50 (2013.01); G06F 17/5045 (2013.01); G06F 17/5068 (2013.01); G06F 2217/40 (2013.01);
Abstract
The invention provides a method of designing an integrated circuit. The method includes providing a physical layout group including a first layout corresponding to a first die having a first function. A second layout corresponds to an interposer configured for the first die connected thereon. The first physical layout group is partitioned into a first physical layout partition according to the first function. A first automatic place-and-route (APR) process is performed to obtain a first hierarchical layout according to the first physical layout partition. A first verification is performed on the first hierarchical layout.