The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 27, 2018

Filed:

Jan. 21, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Alexander P. Campbell, Ottawa, CA;

Keshav G. Kamble, Fremont, CA (US);

Vijoy A. Pandey, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 12/931 (2013.01); G06F 13/42 (2006.01); G06F 13/38 (2006.01); G06F 21/85 (2013.01); H04L 29/06 (2006.01); H04L 12/46 (2006.01); G06F 13/24 (2006.01); H04L 12/721 (2013.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4282 (2013.01); G06F 13/24 (2013.01); G06F 13/385 (2013.01); G06F 13/4022 (2013.01); G06F 13/4068 (2013.01); G06F 21/85 (2013.01); H04L 12/4633 (2013.01); H04L 12/4641 (2013.01); H04L 45/44 (2013.01); H04L 49/351 (2013.01); H04L 63/08 (2013.01); G06F 2213/2424 (2013.01); H04L 63/162 (2013.01);
Abstract

In one embodiment, a method includes receiving a request from a remote distributed fabric protocol (DFP) system master, using a dedicated processor of a DFP system member, to register local IC devices on the DFP system member, and sending an acknowledgement including a list of local IC bus devices back to the DFP system master using the dedicated processor of the DFP system member. The acknowledgement present on the DFP system member. In another embodiment, a system includes a local processor, one or more local IC bus devices, and a dedicated processor electrically coupled to the local IC bus devices. The dedicated processor is configured to route interrupts from the local IC bus devices to the local processor, and expose the local IC devices to a remote DFP system master by sending details of the local IC bus devices to the remote DFP system master.


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