The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2018

Filed:

Apr. 15, 2016
Applicant:

Bae Systems Information and Electronic Systems Integration Inc., Nashua, NH (US);

Inventors:

Joseph D. Cali, Nashua, NH (US);

Curtis M. Grens, Manchester, NH (US);

Lawrence J. Kushner, Andover, MA (US);

Steven E. Turner, Nashua, NH (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 21/00 (2006.01); H03K 23/00 (2006.01); H03K 21/02 (2006.01); H03K 21/38 (2006.01); H03L 7/197 (2006.01); G06F 7/68 (2006.01); H03K 23/40 (2006.01); G06F 1/08 (2006.01); H03K 23/64 (2006.01); H03K 21/40 (2006.01); H03K 23/58 (2006.01); H03K 23/68 (2006.01); H03K 21/10 (2006.01);
U.S. Cl.
CPC ...
H03K 21/026 (2013.01); H03K 21/38 (2013.01); H03L 7/1974 (2013.01); G06F 1/08 (2013.01); G06F 7/68 (2013.01); H03K 21/00 (2013.01); H03K 21/10 (2013.01); H03K 21/40 (2013.01); H03K 23/00 (2013.01); H03K 23/40 (2013.01); H03K 23/58 (2013.01); H03K 23/64 (2013.01); H03K 23/68 (2013.01);
Abstract

Frequency divider techniques are disclosed which can be used to address two problems: when an incorrect division occurs if the modulus control changes before the divide cycle is complete, and when an incorrect division occurs due to a boundary crossing (e.g., power-of-2 boundary crossing in a fractional-N PLL application). In one embodiment, a frequency divider is provided comprising a plurality of flip-flops operatively coupled to carry out division of an input frequency, and configured to generate a modulus output and receive a divided clock signal of a previous cell. An additional flip-flop is selectively clocked off one of the modulus output or the divided clock of the previous stage, depending at least in part on a Skip control signal applied to a data input of the additional flip-flop, and is further configured to selectively reset the plurality of flip-flops to a state that will result in a correct divide ratio.


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