The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2018

Filed:

Nov. 21, 2016
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Kazuhiro Koudate, Tokyo, JP;

Assignee:

RENESAS ELECTRONICS CORPORATION, Kawasaki-Shi, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/018 (2006.01); H03K 19/0185 (2006.01); H03K 19/00 (2006.01); H03K 19/0175 (2006.01); H03K 3/356 (2006.01); H03K 19/003 (2006.01);
U.S. Cl.
CPC ...
H03K 19/018521 (2013.01); H03K 3/356113 (2013.01); H03K 19/0013 (2013.01); H03K 19/00315 (2013.01); H03K 19/017509 (2013.01);
Abstract

A level shifter includes a first and a second transistor coupled to a first power supply voltage terminal supplied with a second power supply voltage in parallel, the first transistor having a first gate connected to a drain of the second transistor and a first gate insulating film, and the second transistor having a second gate connected to a drain of the first transistor and a second gate insulating film, a third and a fourth transistor coupled to a reference voltage terminal in parallel, the third transistor having a third gate supplied with a first control signal and a third gate insulating film, and the fourth transistor having a fourth gate supplied with a second control signal and a fourth gate insulating film, a first and a second depression transistor, and a timing control unit placed between a second power supply voltage terminal and the reference voltage terminal.


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