The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 20, 2018
Filed:
Jul. 29, 2014
Japan Science and Technology Agency, Saitama, JP;
Hidetoshi Onodera, Kyoto, JP;
Islam A. K. M Mahfuzul, Kyoto, JP;
JAPAN SCIENCE AND TECHNOLOGY AGENCY, Saitama, JP;
Abstract
A delay circuit contains a first inversion circuit including a pull-up circuit and a pull-down circuit, and a second inversion circuit including a pull-up circuit and a pull-down circuit. The delay circuit further contains a first pass transistor connected in series to the pull-up circuit in the first inversion circuit between a power supply potential and an output node, a second pass transistor connected in series to the pull-down circuit in the first inversion circuit between a ground potential and the output node, a third pass transistor connected in series between the input node and the pull-up circuit in the second inversion circuit, and a fourth pass transistor connected in series between the input node and the pull-down circuit in the second inversion circuit. A delay characteristic of the delay circuit is changed by a combination of control signals applied to gates of the pass transistors.