The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2018

Filed:

Apr. 13, 2016
Applicant:

Lsis Co., Ltd., Gyeonggi-do, KR;

Inventor:

Hak-Jun Lee, Gyeonggi-do, KR;

Assignee:

LSIS CO., LTD., Anyang-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 7/5387 (2007.01); H02M 7/44 (2006.01); H02M 1/12 (2006.01); H02P 27/08 (2006.01); H02M 1/00 (2006.01); H02M 7/483 (2007.01); H02M 7/497 (2007.01);
U.S. Cl.
CPC ...
H02M 7/44 (2013.01); H02M 1/12 (2013.01); H02M 7/53873 (2013.01); H02P 27/08 (2013.01); H02P 27/085 (2013.01); H02M 7/483 (2013.01); H02M 7/497 (2013.01); H02M 2001/0025 (2013.01); H02M 2007/53876 (2013.01); H02P 2209/13 (2013.01);
Abstract

In one embodiment, an offset voltage generator includes a first limiter configured to compare a first phase-voltage signal with a maximum limit value and a minimum limit value to output a first limit-voltage signal; a second limiter configured to compare a second phase-voltage signal with the maximum limit value and the minimum limit value to output a second limit-voltage signal; a third limiter configured to compare a third phase-voltage signal with the maximum limit value and the minimum limit value to output a third limit-voltage signal; and a summer configured to add a difference between the first phase-voltage signal and the first limit-voltage signal, a difference between the second phase-voltage signal and the second limit-voltage signal, and a difference between the third phase-voltage signal and the third limit-voltage signal, to output an offset voltage.


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