The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2018

Filed:

Aug. 29, 2016
Applicant:

Vidatronic Inc., College Station, TX (US);

Inventor:

Anand Veeravalli Raghupathy, Plano, TX (US);

Assignee:

Vidatronic, Inc., College Station, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 3/07 (2006.01); G05F 1/56 (2006.01); H02M 1/00 (2006.01);
U.S. Cl.
CPC ...
H02M 3/07 (2013.01); G05F 1/56 (2013.01); H02M 2001/0045 (2013.01);
Abstract

A charge pump driven Linear Voltage Regulator (LVR) system with a cascoded n-type output pass device includes an error amplifier; a voltage feedback network; a dynamically controlled charge pump block that is ON only when required and OFF otherwise; a gate drive system configured to ensure that the charge pump drives only gate of a cascode transistor and no DC or static current load such that a voltage is preserved for a duration; and a filter at the charge pump output to reduce an impact of the switching noise of the charge pump on the regulator output, wherein the filter is outside a main servo loop of the regulator, wherein an n-type pass element and/or cascode element in the cascoded n-type output pass device comprises at least one of a Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET), a bipolar junction transistor, an LDMOS, or a FinFET device.


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