The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2018

Filed:

Oct. 22, 2015
Applicant:

Shenzhen China Star Optoelectronics Technology Co., Ltd., Shenzhen, Guangdong, CN;

Inventor:

Jinming Li, Guangdong, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 21/467 (2006.01); H01L 29/66 (2006.01); H01L 23/31 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7869 (2013.01); H01L 21/467 (2013.01); H01L 23/3171 (2013.01); H01L 29/41733 (2013.01); H01L 29/66742 (2013.01);
Abstract

A TFT includes a substrate, a gate, a gate insulating layer, a semiconductor oxide layer, a source/drain layer, a passivation layer, and a transparent conducting layer arranged from bottom to top. An etching block layer is formed after the source/drain layer arranged on the semiconductor oxide layer is etched. A method for forming for the TFT includes: depositing and photo-etching a gate on a substrate; depositing a gate insulating layer on the gate; depositing and photo-etching a semiconductor oxide layer on the gate insulating layer; depositing and photo-etching a source/drain layer on the semiconductor oxide layer; etching the source/drain layer on the semiconductor oxide layer for forming an etching block layer; depositing a passivation layer on the source/drain layer and the semiconductor oxide layer; depositing a transparent conducting layer on the passivation layer.


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