The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2018

Filed:

Mar. 09, 2016
Applicant:

Lapis Semiconductor Co., Ltd., Yokohama, JP;

Inventors:

Yasuo Arai, Ibaraki, JP;

Masao Okihara, Tokyo, JP;

Hiroki Kasai, Miyagi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 27/146 (2006.01); H01L 21/265 (2006.01); H01L 27/144 (2006.01); H01L 29/861 (2006.01); H01L 21/225 (2006.01); H01L 21/84 (2006.01); H01L 29/66 (2006.01); H01L 27/06 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14658 (2013.01); H01L 21/225 (2013.01); H01L 21/2652 (2013.01); H01L 21/84 (2013.01); H01L 27/1203 (2013.01); H01L 27/1207 (2013.01); H01L 27/1443 (2013.01); H01L 27/1461 (2013.01); H01L 27/14612 (2013.01); H01L 29/66477 (2013.01); H01L 29/8611 (2013.01); H01L 27/0629 (2013.01); H01L 29/78648 (2013.01);
Abstract

There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.


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