The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2018

Filed:

Mar. 03, 2016
Applicant:

Marvell Israel (M.i.s.l) Ltd., Yokneam, IL;

Inventors:

Amir Bishara, Tel-Aviv Jaffa, IL;

Lior Valency, Tel-Aviv, IL;

Rami Zemach, Givat Shapira, IL;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/28 (2006.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 13/287 (2013.01); G06F 13/1663 (2013.01); G06F 13/4234 (2013.01);
Abstract

Aspects of the disclosure provide a circuit that includes a plurality of memory access circuits configured to access a memory to read or write data of a first width. The memory includes a plurality of memory banks that are organized in hierarchy. Further, the circuit includes a plurality of interface circuits respectively associated with the plurality of memory access circuits. Each interface circuit is configured to receive memory access requests to first level memory banks from an associated memory access circuit, segment the memory access requests into sub-requests to corresponding second level memory banks, buffer the sub-requests into buffers associated with the second level memory banks. In addition, the circuit includes arbitration circuitry configured to control multiplexing paths from the buffers to the second level memory banks to enable, in a same memory access clock, memory accesses by the memory access circuits.


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