The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2018

Filed:

Nov. 17, 2014
Applicant:

Sandisk Technologies Inc., Plano, TX (US);

Inventors:

James M. Higgins, Chandler, AZ (US);

Robert W. Ellis, Phoenix, AZ (US);

Neil R. Darragh, Edinburgh, GB;

Aaron K. Olbrich, Morgan Hill, CA (US);

Navneeth Kankani, Fremont, CA (US);

Steven Sprouse, San Jose, CA (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G11C 16/10 (2006.01); G11C 29/52 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/34 (2006.01); G11C 8/08 (2006.01); G11C 29/02 (2006.01); G11C 29/42 (2006.01); G11C 13/00 (2006.01); G11C 29/12 (2006.01); H01L 27/11582 (2017.01);
U.S. Cl.
CPC ...
G06F 11/1072 (2013.01); G11C 8/08 (2013.01); G11C 11/5628 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/3404 (2013.01); G11C 16/349 (2013.01); G11C 29/025 (2013.01); G11C 29/028 (2013.01); G11C 29/42 (2013.01); G11C 29/52 (2013.01); G11C 13/0002 (2013.01); G11C 2029/1202 (2013.01); G11C 2211/5641 (2013.01); G11C 2213/71 (2013.01); H01L 27/11582 (2013.01);
Abstract

A memory controller configures a plurality of word lines associated with a respective block of a 3D memory device in a first configuration, where the first configuration includes a set of configuration parameters for each word line of the plurality of word lines determined at least in part on the vertical positions of each word line relative to a substrate of the 3D memory device and, while the plurality of word lines are configured in the first configuration, writes data to and reads data from the respective block. For the respective block, the memory controller: adjusts a first parameter in the respective set of configuration parameters corresponding to a respective word line of the plurality of word lines in response to detecting a first trigger condition as to the respective word line and, after adjusting the first parameter, writes data to and reads data from the respective word line.


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