The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2018

Filed:

Nov. 02, 2015
Applicant:

Ip Reservoir, Llc, St. Louis, MO (US);

Inventors:

Roger D. Chamberlain, St. Louis, MO (US);

Mark Allen Franklin, St. Louis, MO (US);

Ronald S. Indeck, St. Louis, MO (US);

Ron K. Cytron, St. Louis, MO (US);

Sharath R. Cholleti, Saint Paul, MN (US);

Assignee:

IP RESERVOIR, LLC, St. Louis, MO (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/30 (2006.01); G06F 9/445 (2018.01); G06F 21/60 (2013.01); G06F 21/72 (2013.01); G06F 21/76 (2013.01); G06F 21/85 (2013.01); G06Q 40/06 (2012.01); G06F 17/00 (2006.01); G06F 9/48 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 9/44505 (2013.01); G06F 3/061 (2013.01); G06F 3/067 (2013.01); G06F 3/0655 (2013.01); G06F 3/0683 (2013.01); G06F 9/4881 (2013.01); G06F 17/00 (2013.01); G06F 17/30477 (2013.01); G06F 21/602 (2013.01); G06F 21/72 (2013.01); G06F 21/76 (2013.01); G06F 21/85 (2013.01); G06Q 40/06 (2013.01); G06F 3/0601 (2013.01); G06F 2003/0692 (2013.01);
Abstract

Methods and systems are disclosed where a plurality of precompiled hardware templates are stored in memory, each of the hardware templates being configured for loading onto a re-configurable logic device such as a FPGA to define a data processing operation to be performed by the re-configurable logic device, each of the data processing operations defined by the precompiled hardware templates having an associated performance characteristic. A processor selects a precompiled hardware template from a plurality of the precompiled hardware templates in the memory for loading onto the re-configurable logic device based at least in part on the associated performance characteristics of the data processing operations defined by the precompiled hardware templates.


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