The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2018

Filed:

Feb. 25, 2016
Applicant:

Mireplica Technology, Llc, Austin, TX (US);

Inventor:

William M. Johnson, Austin, TX (US);

Assignee:

Mireplica Technology, LLC, Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2006.01); G06T 1/20 (2006.01); G06F 9/38 (2006.01); G06F 15/76 (2006.01); G06F 9/455 (2006.01); G06F 15/80 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3016 (2013.01); G06F 9/3017 (2013.01); G06F 9/3881 (2013.01); G06F 9/3893 (2013.01); G06F 9/4552 (2013.01); G06F 15/76 (2013.01); G06F 15/80 (2013.01); G06T 1/20 (2013.01);
Abstract

Methods, devices and systems are disclosed that interface a host computer to a specialized processor. In an embodiment, an instruction generation unit comprises attribute, decode, and instruction buffer stages. The attribute stage is configured to receive a host-program operation code and a virtual host-program operand from the host computer and to expand the virtual host-program operand into an operand descriptor. The decode stage is configured to receive the first operand descriptor and the host-program operation code, convert the host-program operation code to one or more decoded instructions for execution by the specialized processor, and allocate storage locations for use by the specialized processor. The instruction buffer stage is configured to receive the decoded instruction, place the one or more decoded instructions into one or more instruction queues, and issue decoded instructions from at least one of the one or more instruction queues for execution by the specialized processor.


Find Patent Forward Citations

Loading…