The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 13, 2018
Filed:
Dec. 17, 2013
International Business Machines Corporation, Armonk, NY (US);
Derek Robertson, Durham, NC (US);
Vincent M. Rogers, Raleigh, NC (US);
Lenovo Enterprise Solutions (Singapore) Pte. Ltd., Singapore, SG;
Abstract
Embodiments of the invention relates to adding test access to a back-drilled vertical access interconnect (VIA) of a printed circuit board (PCB). A VIA is either formed or provided as an opening through layers of the PCB. The VIA is countersunk from one of the two openings to the PCB prior to plating to form a surface that can be used as a test target. The countersunk VIA is subject to plating so that the interior walls and surfaces of the VIA are covered with a conductive material. The plating is removed along the walls of the countersunk section of the VIA, so that the plating remains on the shoulders and the non-countersunk section of the VIA with the shoulder in communication with a trace internal to the PCB. The back-drilled VIA with the plating configuration provides an internal conducting surface for contact while mitigating interference associated with a VIA stub.