The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 13, 2018
Filed:
Feb. 09, 2016
Applicant:
Hitachi Metals, Ltd., Minato-ku, Tokyo, JP;
Inventors:
Kazutoshi Kariya, Tsuchiura, JP;
Shingo Sugawara, Tsuchiura, JP;
Assignee:
Hitachi Metals, Ltd., Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/28 (2006.01); H04L 12/56 (2006.01); H04L 12/741 (2013.01); H04L 12/18 (2006.01); H04L 12/46 (2006.01); H04L 12/705 (2013.01);
U.S. Cl.
CPC ...
H04L 45/74 (2013.01); H04L 12/18 (2013.01); H04L 12/4625 (2013.01); H04L 12/4645 (2013.01); H04L 45/18 (2013.01);
Abstract
An LP table retains a combination of a physical port and a VLAN identifier in association with a logical port. When a frame is received at the physical port, a table processing unit acquires a logical port based on the LP table. An FDB processing unit learns a source MAC address contained in the received frame in association with the logical port acquired by the table processing unit to an FDB. A plurality of logical ports are set for the physical port by the LP table. A loop prevention unit prohibits frame relay between the plurality of logical ports set for the physical port.