The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2018

Filed:

Jul. 01, 2016
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Subhashish Mukherjee, Bangalore, IN;

Abhijit Anant Patki, Bangalore, IN;

Madhulatha Bonu, Bangalore, IN;

Kumar Anurag Shrivastava, Bangalore, IN;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H04L 27/22 (2006.01); H03L 7/087 (2006.01); H03L 7/113 (2006.01); H03K 19/21 (2006.01); H04L 7/033 (2006.01);
U.S. Cl.
CPC ...
H04L 27/22 (2013.01); H03K 19/21 (2013.01); H03L 7/087 (2013.01); H03L 7/113 (2013.01); H04L 7/0087 (2013.01); H04L 7/0331 (2013.01);
Abstract

Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase; when the data signal is oscillating at the first phase, output a first logic value; and when the data signal is oscillating at the second phase, output a second logic value, the output of the fast phase change detection circuit being used to determine whether the first output signal or the second output signal will be utilized in the feedback loop of the low bandwidth phase lock loop.


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