The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 13, 2018
Filed:
Sep. 23, 2015
Mediatek Inc., Hsin-Chu, TW;
MEDIATEK INC., Hsin-Chu, TW;
Abstract
A wideband highly-linear buffer circuit exhibiting a low output impedance comprises a first PFET (PFET), a second PFET (PFET), a first NFET (NFET), and a second NFET (NFET). Sources of PFETand PFETare coupled to VDD. PFET's drain is coupled to an output lead. PFETacts as a current source. NFET's drain is coupled to PFET's drain and to PFET's gate. NFET's source is coupled to the output lead. NFET's source is coupled to ground. NFET's drain is coupled to NFET's source and to the output lead. NFET's gate is AC coupled to a first input lead. In a single-ended input example, NFET's gate is AC coupled NFET's drain. In a differential input example, NFET's gate is AC coupled to a second input lead. In another differential input example, PFETis not just a current source, but rather PFET's gate is AC coupled to the first input lead.