The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2018

Filed:

Jul. 11, 2016
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Dong-Seok Lee, Suwon-si, KR;

Woo-Seok Kim, Suwon-si, KR;

Jae-Jin Park, Seongnam-si, KR;

Dong-Hyuk Lim, Seoul, KR;

Dae-Young Chung, Seoul, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/1534 (2006.01); H04L 7/00 (2006.01); H03K 19/21 (2006.01); H01L 27/118 (2006.01);
U.S. Cl.
CPC ...
H03K 5/1534 (2013.01); H03K 19/21 (2013.01); H04L 7/0037 (2013.01); H04L 7/0087 (2013.01); H01L 27/11803 (2013.01); H01L 2027/11881 (2013.01);
Abstract

An edge detector includes a differential signal generator, a sense amplifier and a latch. The differential signal generator delays an input signal to generate a first differential signal and inverts the input signal to generate a second differential signal. The sense amplifier amplifies a difference between the first differential signal and the second differential signal to generate a first amplification signal and a second amplification signal at a first edge of a test clock signal and resets the first amplification signal and the second amplification signal at a second edge of the test clock signal. The latch generates an edge signal corresponding to edge information of the input signal in response to the first amplification signal and the second amplification signal.


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