The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2018

Filed:

Dec. 15, 2014
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Ranabir Dey, Bangalore, IN;

Abhinav Kumar, Bangalore, IN;

Vijaya Kumar Vinukonda, Bangalore, IN;

Fabrice Blanc, Grenoble, FR;

Assignee:

ARM Limited, Cambridge, GB;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H02H 9/00 (2006.01); H02H 9/04 (2006.01); H01L 29/78 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H02H 9/046 (2013.01); H01L 27/0285 (2013.01); H01L 29/78 (2013.01);
Abstract

Various implementations described herein are directed to an integrated circuit for electrostatic discharge (ESD) protection. The integrated circuit may include a detection stage having a resistor and a first capacitor cascaded with a second capacitor. The resistor and the first capacitor are arranged to define a triggering node configured to provide a triggering signal. The first capacitor and the second capacitor are arranged to define a reference node configured to provide a reference signal. The integrated circuit may include a first ESD clamping stage having a first transistor configured to provide a supply voltage to a first clamping transistor based on the triggering signal. The integrated circuit may include a second ESD clamping stage having a second transistor configured to receive the supply voltage from the first transistor and provide the supply voltage to a second clamping transistor based on the reference signal.


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