The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2018

Filed:

Apr. 20, 2017
Applicant:

Optiz, Inc., Palo Alto, CA (US);

Inventors:

Vage Oganesian, Sunnyvale, CA (US);

Zhenhua Lu, Suzhou, CN;

Assignee:

Optiz, Inc., Palo Alto, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/02 (2006.01); H01L 27/146 (2006.01); H01L 31/0203 (2014.01);
U.S. Cl.
CPC ...
H01L 31/02002 (2013.01); H01L 27/14618 (2013.01); H01L 27/14636 (2013.01); H01L 27/14683 (2013.01); H01L 31/0203 (2013.01);
Abstract

A packaged chip assembly with a semiconductor substrate, a semiconductor device integrally formed on or in the substrate's top surface, and first bond pads at the substrate's top surface electrically coupled to the semiconductor device. A second substrate includes a first aperture and one or more second apertures extending therethrough, second and third bond pads at the second substrate's top and bottom surfaces, respectively, and conductors electrically coupled to the second and third bond pads. The semiconductor substrate's top surface is secured to the second substrate's bottom surface such that the semiconductor device is aligned with the first aperture, and each of the first bond pads is aligned with one of the second apertures. A plurality of wires are each electrically connected between one of the first bond pads and one of the second bond pads and each passing through one of the one or more second apertures.


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