The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2018

Filed:

May. 23, 2014
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Heecheol Kim, Beijing, CN;

Youngsuk Song, Beijing, CN;

Seongyeol Yoo, Beijing, CN;

Seungjin Choi, Beijing, CN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G02F 1/1362 (2006.01); H01L 27/12 (2006.01); G02F 1/1333 (2006.01); G02F 1/1343 (2006.01); G02F 1/1368 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 27/124 (2013.01); G02F 1/1368 (2013.01); G02F 1/13439 (2013.01); G02F 1/133345 (2013.01); G02F 1/136227 (2013.01); G02F 1/136286 (2013.01); H01L 27/1222 (2013.01); H01L 27/1259 (2013.01); H01L 29/66765 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78669 (2013.01); H01L 29/78678 (2013.01); G02F 2001/136295 (2013.01);
Abstract

An array substrate and a fabrication method thereof, and a display device are provided. The array substrate comprises a gate line and a data line intersecting with each other. The data line and the gate line are formed in a same layer on a substrate, the data line is disconnected in a region of the gate line. A connection pattern is formed in the region of the gate line, the connection pattern is insulated from the gate line, and ends of the data line located on both sides of the gate line are electrically connected by the connection pattern.


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