The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2018

Filed:

Feb. 22, 2016
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Phil Ouk Nam, Suwon-si, KR;

Yong Hoon Son, Yongin-si, KR;

Kyung Hyun Kim, Seoul, KR;

Byeong Ju Kim, Hwaseong-si, KR;

Kwang Chul Park, Suwon-si, KR;

Yeon Sil Sohn, Yongin-si, KR;

Jin I Lee, Hwaseong-si, KR;

Jong Heun Lim, Hwaseong-si, KR;

Won Bong Jung, Seoul, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/84 (2006.01); H01L 21/20 (2006.01); H01L 21/36 (2006.01); H01L 29/10 (2006.01); H01L 29/76 (2006.01); H01L 31/036 (2006.01); H01L 31/112 (2006.01); H01L 27/1157 (2017.01); H01L 21/02 (2006.01); H01L 27/11573 (2017.01); H01L 27/11582 (2017.01);
U.S. Cl.
CPC ...
H01L 27/1157 (2013.01); H01L 21/02667 (2013.01); H01L 21/02675 (2013.01); H01L 27/11573 (2013.01); H01L 27/11582 (2013.01);
Abstract

A memory device, including a first memory region including a first substrate, a plurality of first semiconductor devices on the first substrate, and a first interlayer insulating layer covering the plurality of first semiconductor devices; and a second memory region including a second substrate on the first interlayer insulating layer and a plurality of second semiconductor devices on the second substrate, the second substrate including a first region in a plurality of grooves in the first interlayer insulating layer and a second region including grains extending from the first region, the second region being on an upper surface of the first interlayer insulating layer.


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