The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2018

Filed:

May. 29, 2014
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Tian San Tan, Melaka, MY;

Theng Chao Long, Melaka, MY;

Ming Kai Benny Goh, Melaka, MY;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 23/46 (2006.01); H01L 21/48 (2006.01); H01L 21/52 (2006.01); H01L 21/56 (2006.01); H01L 29/739 (2006.01); H01L 29/78 (2006.01); H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/473 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3672 (2013.01); H01L 21/4871 (2013.01); H01L 21/4882 (2013.01); H01L 21/52 (2013.01); H01L 21/56 (2013.01); H01L 23/3675 (2013.01); H01L 23/46 (2013.01); H01L 23/49524 (2013.01); H01L 23/49562 (2013.01); H01L 23/49568 (2013.01); H01L 24/40 (2013.01); H01L 29/7395 (2013.01); H01L 29/7802 (2013.01); H01L 23/3107 (2013.01); H01L 23/473 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/40245 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/181 (2013.01);
Abstract

A semiconductor packaging system includes a semiconductor device package having a semiconductor chip with two or more terminals and a protective structure encapsulating and electrically insulating the semiconductor chip. Two or more electrical conductors that are each electrically connected to one of the terminals extend to an outer surface of the protective structure. A first surface feature is on an exterior surface of the semiconductor device package. The system further includes a connectable package extender having a second surface feature configured to interlock with the first surface feature when the first surface feature is mated with the second surface feature so as to secure the package extender to the semiconductor device package. An extension portion adjoins and extends away from the exterior surface of the semiconductor device package when the package extender is secured to the semiconductor device package.


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