The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 13, 2018
Filed:
Sep. 20, 2016
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Inventors:
Sang Woo Pae, Seongnam-si, KR;
Hyun Chul Sagong, Hwaseong-si, KR;
Jin Ju Kim, Bucheon-si, KR;
June Kyun Park, Seongnam-si, KR;
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/82 (2006.01); H01L 21/30 (2006.01); H01L 29/66 (2006.01); H01L 21/8238 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823821 (2013.01); H01L 21/3081 (2013.01); H01L 21/31111 (2013.01); H01L 21/32139 (2013.01); H01L 21/823828 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01);
Abstract
A method of generating a fin of a FinFET includes depositing a first hard mask layer on or above a first dummy gate and a second dummy gate, generating first spacers and second spacers by etching the first hard mask layer, removing only the first spacers, depositing a second hard mask layer, generating third spacers and fourth spacers by etching the second hard mask layer, removing the first dummy gate and the second dummy gate, generating first fins using the third spacers, and generating second fins using the second spacers and the fourth spacers.