The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2018

Filed:

Oct. 15, 2015
Applicant:

Via Technologies, Inc., New Taipei, TW;

Inventors:

G. Glenn Henry, Austin, TX (US);

Terry Parks, Austin, TX (US);

Brent Bean, Austin, TX (US);

Thomas A. Crispin, Austin, TX (US);

Assignee:

VIA TECHNOLOGIES, INC., New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/72 (2013.01); G06F 9/30 (2006.01); H04L 9/08 (2006.01); G06F 21/74 (2013.01); G06F 12/0875 (2016.01); G06F 21/52 (2013.01); G06F 21/60 (2013.01); G06F 21/71 (2013.01); H04L 9/06 (2006.01);
U.S. Cl.
CPC ...
G06F 21/72 (2013.01); G06F 9/30003 (2013.01); G06F 9/30079 (2013.01); G06F 9/30178 (2013.01); G06F 9/30189 (2013.01); G06F 12/0875 (2013.01); G06F 21/52 (2013.01); G06F 21/602 (2013.01); G06F 21/71 (2013.01); G06F 21/74 (2013.01); H04L 9/0618 (2013.01); H04L 9/0861 (2013.01); H04L 9/0891 (2013.01); H04L 9/0894 (2013.01); G06F 2212/402 (2013.01); G06F 2212/452 (2013.01); G06F 2221/2107 (2013.01); H04L 2209/12 (2013.01); H04L 2209/20 (2013.01);
Abstract

A microprocessor and method are provided for securely decrypting and executing encrypted instructions within a microprocessor. A plurality of master keys are stored in a secure memory. Encrypted instructions are fetched from an instruction cache. A set of one or more master keys are selected from the secure memory based upon an encrypted instruction fetch address. The selected set of master keys or a decryption key derived therefrom is used to decrypt the encrypted instructions fetched from the instruction cache. The decrypted instructions are then securely executed within the microprocessor. In one implementation, the master keys are intervolved with each other to produce a new decryption key with every fetch quantum. Moreover, a new set of master keys is selected with every new block of instructions.


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