The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2018

Filed:

Sep. 17, 2009
Applicants:

Jari Nikara, Lempaala, FI;

Eero Aho, Tampere, FI;

Kimmo Kuusilinna, Tampere, FI;

Inventors:

Jari Nikara, Lempaala, FI;

Eero Aho, Tampere, FI;

Kimmo Kuusilinna, Tampere, FI;

Assignee:

Provenance Asset Group LLC, Essex, CT (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/0842 (2016.01); G06F 12/08 (2016.01); G06F 12/0846 (2016.01); G06F 12/084 (2016.01); G06F 12/0844 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0846 (2013.01); G06F 12/084 (2013.01); G06F 12/0842 (2013.01); G06F 12/0844 (2013.01);
Abstract

A cache memory including: a plurality of parallel input ports configured to receive, in parallel, memory access requests wherein each parallel input port is operable to receive a memory access request for any one of a plurality of processing units; and a plurality of cache blocks wherein each cache block is configured to receive memory access requests from a unique one of the plurality of input ports such that there is a one-to-one mapping between the plurality of parallel input ports and the plurality of cache blocks and wherein each of the plurality of cache blocks is configured to serve a unique portion of an address space of the memory.


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