The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2018

Filed:

Aug. 09, 2016
Applicant:

Via Technologies, Inc., New Taipei, TW;

Inventors:

G. Glenn Henry, Austin, TX (US);

Stephan Gaskins, Austin, TX (US);

Assignee:

VIA TECHNOLOGIES, INC., New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/76 (2006.01); G06F 1/04 (2006.01); G06F 1/12 (2006.01); G06F 9/38 (2006.01); G06F 1/32 (2006.01); G06F 12/084 (2016.01); G06F 13/24 (2006.01); G06F 9/44 (2006.01); G06F 13/364 (2006.01); G06F 12/0808 (2016.01); G06F 9/30 (2006.01); G06F 12/0875 (2016.01); G06F 13/42 (2006.01); G06F 21/53 (2013.01); G06F 21/57 (2013.01); H04L 9/08 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3885 (2013.01); G06F 1/04 (2013.01); G06F 1/12 (2013.01); G06F 1/3203 (2013.01); G06F 1/324 (2013.01); G06F 1/3237 (2013.01); G06F 1/3287 (2013.01); G06F 1/3296 (2013.01); G06F 9/30032 (2013.01); G06F 9/30047 (2013.01); G06F 9/30079 (2013.01); G06F 9/30087 (2013.01); G06F 9/30105 (2013.01); G06F 9/30145 (2013.01); G06F 9/3802 (2013.01); G06F 9/3861 (2013.01); G06F 9/4403 (2013.01); G06F 9/4405 (2013.01); G06F 9/4411 (2013.01); G06F 9/4418 (2013.01); G06F 12/084 (2013.01); G06F 12/0808 (2013.01); G06F 12/0875 (2013.01); G06F 13/24 (2013.01); G06F 13/364 (2013.01); G06F 13/42 (2013.01); G06F 21/53 (2013.01); G06F 21/57 (2013.01); G06F 2212/452 (2013.01); G06F 2212/6028 (2013.01); G06F 2212/62 (2013.01); H01L 22/34 (2013.01); H04L 9/0877 (2013.01); H04L 9/0897 (2013.01); Y02B 60/1217 (2013.01); Y02B 60/1221 (2013.01); Y02B 60/1282 (2013.01); Y02B 60/1285 (2013.01); Y02B 60/32 (2013.01);
Abstract

A microprocessor a plurality of processing cores, wherein each of the plurality of processing cores instantiates a respective architecturally-visible storage resource. A first core of the plurality of processing cores is configured to encounter an architectural instruction that instructs the first core to update the respective architecturally-visible storage resource of the first core with a value specified by the architectural instruction. The first core is further configured to, in response to encountering the architectural instruction, provide the value to each of the other of the plurality of processing cores and update the respective architecturally-visible storage resource of the first core with the value. Each core of the plurality of processing cores other than the first core is configured to update the respective architecturally-visible storage resource of the core with the value provided by the first core without encountering the architectural instruction.


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