The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2018

Filed:

Jun. 15, 2015
Applicant:

Altera Corporation, San Jose, CA (US);

Inventors:

Ru Yin Ng, Bayan Lepas, MY;

Gary Wallichs, San Jose, CA (US);

Keith Duwel, San Jose, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/10 (2006.01); G06F 1/12 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 1/10 (2013.01); G06F 1/12 (2013.01); G06F 13/4278 (2013.01);
Abstract

An integrated circuit die includes interface and adapter circuits. The interface circuit exchanges data with an external device outside the integrated circuit die using a first clock signal. The interface circuit has a clock signal generation circuit to generate the first clock signal based on a second clock signal. The adapter circuit exchanges the data with the interface circuit. A frequency of the second clock signal is changed in response to an indication of a change in a data rate of the data. The adapter circuit causes the interface circuit to provide an adjustment to the first clock signal after the frequency of the second clock signal changes. The adapter circuit prevents the exchange of the data between the interface circuit and the external device until the adapter circuit receives an indication of completion of the adjustment to the first clock signal.


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