The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2018

Filed:

May. 17, 2015
Applicant:

B. G. Negev Technologies and Applications Ltd., AT Ben Gurion University, Beer Sheva, IL;

Inventors:

Mor Mordechai Peretz, Lehavim, IL;

Yevgeny Bezdenezhnykh, Beer Sheva, IL;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/50 (2006.01); G04F 10/00 (2006.01);
U.S. Cl.
CPC ...
G04F 10/005 (2013.01);
Abstract

The present invention relates to the realization of an ADC by using a one shot time cell as an analog-to-time converter and a time-to-digital converter. The present invention relates in general, to the design and Integrated Circuit (IC) implementation of a fully-digital fully-synthesizable, delay-line analog-to-digital converter (DL-ADC). The present invention is specifically relevant for power management applications where the silicon area of the controller is of key importance. The design of the ADC is based on the approach of delay cells string to reduce design complexity and the resultant of the silicon area.


Find Patent Forward Citations

Peretz, Mor. (2018). Fully-digital fully-synthesizable delay-line analog to digital converter (U.S. Patent No. 9891593). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9891593

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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