The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 13, 2018
Filed:
Sep. 14, 2016
AU Optronics Corporation, Hsin-chu, TW;
Hsiang-Yun Hsiao, Hsin-chu, TW;
Chia-Kai Chen, Hsin-chu, TW;
Shih-Liang Lin, Hsin-chu, TW;
Ting-Yu Hsu, Hsin-chu, TW;
Pei-Yun Wang, Hsin-chu, TW;
Ya-Qin Huang, Hsin-chu, TW;
Cheng-Wei Jiang, Hsin-chu, TW;
AU OPTRONICS CORPORATION, Hsin-Chu, TW;
Abstract
A method of fabricating a polycrystalline silicon thin film transistor device includes the following steps. A substrate is provided, and a buffer layer having dopants is formed on the substrate. An amorphous silicon layer is formed on the buffer layer having the dopants. A thermal process is performed to convert the amorphous silicon layer into a polycrystalline silicon layer by means of polycrystalization, and to simultaneously out-diffuse a portion of the dopants in the buffer layer into the polycrystalline silicon layer for adjusting a threshold voltage. The polycrystalline silicon layer is patterned to form an active layer. A gate insulating layer is formed on the active layer. A gate electrode is formed on the gate insulating layer. A source doped region and a drain doped region are formed in the active layer.