The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 06, 2018

Filed:

Oct. 04, 2013
Applicant:

Lg Innotek Co., Ltd., Seoul, KR;

Inventors:

Sang Myung Lee, Seoul, KR;

Byeong Ho Kim, Seoul, KR;

Jae Seok Park, Seoul, KR;

Yeong Uk Seo, Seoul, KR;

Hyun Seok Seo, Seoul, KR;

Chang Woo Yoo, Seoul, KR;

Kyu Won Lee, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/09 (2006.01); H05K 1/03 (2006.01); H05K 3/10 (2006.01); H05K 3/40 (2006.01); H05K 3/46 (2006.01); H05K 1/02 (2006.01); H05K 1/11 (2006.01); H05K 3/00 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0346 (2013.01); H05K 1/0298 (2013.01); H05K 1/0366 (2013.01); H05K 1/0373 (2013.01); H05K 1/115 (2013.01); H05K 1/119 (2013.01); H05K 3/107 (2013.01); H05K 3/4007 (2013.01); H05K 3/465 (2013.01); H05K 3/0032 (2013.01); H05K 2201/0367 (2013.01); H05K 2201/096 (2013.01); H05K 2203/041 (2013.01);
Abstract

A printed circuit board includes a core insulating layer including an isotropic resin, a first circuit pattern filled in a circuit pattern groove at an upper portion or a lower portion of the core insulating layer, a first insulating layer provided in a top surface thereof with a circuit pattern groove and covering the first circuit pattern, and a second circuit pattern to fill the circuit pattern groove of the first insulating layer. A material, such as polyimide, having an isotropic structure is employed for the core insulating layer, thereby preventing the substrate from being bent without glass fiber. Since the glass fiber is not included, the buried pattern is formed at the upper portion or the lower portion of the core insulating layer, so that the thin substrate is fabricated.


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