The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 06, 2018

Filed:

Sep. 08, 2016
Applicant:

Ross Video Limited, Iroquois, CA;

Inventors:

Scott Raymond Kaneta, Virginia Beach, VA (US);

Desmond Leslie Ambrose, Ottawa, CA;

Christopher Jason Williams, Chesapeake, VA (US);

Assignee:

Ross Video Limited, Iroquois, CA;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 25/03 (2006.01); H04L 25/14 (2006.01); H04N 21/236 (2011.01); H04N 21/434 (2011.01); H04L 7/02 (2006.01);
U.S. Cl.
CPC ...
H04L 25/03 (2013.01); H04L 25/14 (2013.01); H04N 21/23602 (2013.01); H04N 21/4342 (2013.01); H04L 7/02 (2013.01);
Abstract

In an FPGA device, an FPGA receiver is configured to receive a serial signal, to deserialize the received serial signal into a parallel signal, and to align parallel words in the parallel signal. Programmable FPGA fabric in the FPGA device is coupled to receive the parallel signal from the FPGA receiver. The programmable FPGA fabric is also configured to descramble data words from the parallel words in the parallel signal, to perform a phase detection operation based on the descrambled data words, to generate an alignment control signal based on the phase detection operation, and to feed back the alignment control signal to the FPGA receiver to control alignment of the parallel words in the parallel signal. The serial signal is a Serial Digital Interface (SDI) signal in an embodiment.


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