The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 06, 2018
Filed:
Oct. 27, 2016
Applicant:
Andapt, Inc., San Jose, CA (US);
Inventors:
Kapil Shankar, Saratoga, CA (US);
Thomas Chan, Saratoga, CA (US);
Patrick J. Crotty, San Jose, CA (US);
John Birkner, Woodside, CA (US);
Assignee:
AnDAPT, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/177 (2006.01); H03K 19/0175 (2006.01); H02M 3/158 (2006.01);
U.S. Cl.
CPC ...
H03K 19/17772 (2013.01); H02M 3/158 (2013.01); H03K 19/017509 (2013.01); H03K 19/1776 (2013.01); H03K 19/17744 (2013.01);
Abstract
A programmable logic device (PLD) includes a programmable fabric, a plurality of input/output (I/O) blocks, and a plurality of high voltage power field effect transistors (FETs). The PLD can be programmed to connect one or more of the plurality of I/O blocks, one or more of the plurality of high voltage power transistors via the programmable fabric. Each of the plurality of high voltage power transistors includes a drain pad and a source pad that are exposed via external pins of the PLD.