The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 06, 2018
Filed:
Jan. 19, 2015
Sumitomo Electric Industries, Ltd., Osaka-shi, JP;
Katsushi Akita, Itami, JP;
Kei Fujii, Itami, JP;
Takashi Kyono, Itami, JP;
Koji Nishizuka, Itami, JP;
Kaoru Shibata, Itami, JP;
Sumitomo Electric Industries, Ltd., Osaka-shi, JP;
Abstract
A semiconductor layered structure includes a substrate formed of a III-V compound semiconductor, a buffer layer disposed on and in contact with the substrate and formed of a III-V compound semiconductor, and a quantum well layer disposed on and in contact with the buffer layer and including a plurality of component layers formed of III-V compound semiconductors. The substrate has a diameter of 55 mm or more. At least one of the component layers is formed of a mixed crystal of three or more elements. When the compound semiconductor forming the substrate has a lattice constant d, the compound semiconductor forming the buffer layer has a lattice constant d, and the compound semiconductors forming the quantum well layer have an average lattice constant d, (d−d)/dis −3×10or more and 3×10or less, and (d−d)/dis −3×10or more and 3×10or less.